Combat phase-locked loop fractional spurs to improve wireless system performance in 5G and beyond

Two innovative design techniques have significantly improved the performance of fractional-N phase-locked loops (PLLs), Tokyo Tech scientists report.

The proposed method aims to minimize unwanted signals known as fractional spurs that typically plague PLLs used in many modern radar systems and radio transceivers. These efforts could open the door to technological improvements in wireless communications, self-driving cars, and surveillance and tracking systems in the 5G era and beyond.

Many emerging and evolving technologies, such as self-driving cars, target tracking systems, and remote sensors, rely on the fast, error-free operation of wireless data transceivers and radar systems. In these applications, phase-locked loops (PLLs) are key components that help synthesize, modulate, and synchronize oscillating signals. Therefore, eliminating or minimizing sources of PLL error is essential to improving overall system performance.

The main enemy of fractional-N PLLs is a common type of PLL that offers superior resolution and flexible control over frequency, jitter, and fractional spurs. “Jitter” refers to the overall deviation of the synthesized oscillation from ideal timing. Fractional spurs, on the other hand, are unwanted signals resulting from the periodicity of errors.

To cancel quantization errors, digital PLLs typically use a component called a digital time converter (DTC), but imperfections in the DTC due to so-called “integral nonlinearity (INL)” can ultimately appears as a fractional spur that degrades the Noise is generated at the output of the PLL.

A Tokyo Institute of Technology (Tokyo Tech) research team led by Professor Kenichi Okada sought to address these issues through the development of two innovative design techniques that lead to low spurious fractional-N PLLs. Their works are Proceedings of the 2024 IEEE International Solid State Circuits Conference (ISSCC).

The first proposed technique involves the use of cascading fractional dividers. This method splits the frequency control word (FCW), the internal PLL signal that controls the output frequency, into two parts, both of which are far from integer values.

The underlying logic is that for far-integer FCW, fractional spurs appear in the PLL at high frequencies, and the high-frequency components are naturally removed by the inherent behavior of the PLL. Notably, this approach does not include digital predistortion (DPD) techniques, which introduce complexity and introduce phase-lock delays.

The second proposed technique revolves around pseudo-differential DTC to avoid the pitfalls of standard DTC implementations.

“Traditional DTC designs have tight trade-offs between DTC power, delay range, noise, and INL, limiting the minimum achievable fractional spur level,” Professor Okada explains. To address this issue, researchers pointed out that the nonlinearity of DTC even contains a symmetric component. Therefore, they implemented the functionality of a single DTC using two half-range DTCs with the same even symmetrical INL in differential operation. As a result, these INLs were naturally canceled by subtraction in the phase detector of the PLL.

The team tested the idea by implementing the proposed digital PLL using a 65 nm CMOS process that requires only 0.23 mm of active circuit area.². The researchers noticed several advantages by comparing the performance of their device with other state-of-the-art designs.

“By suppressing the fractional spurs, the integrated PLL jitter was reduced from 243.5 fs to 143.7 fs,” says Professor Okada. “Thanks to the proposed cascaded fractional divider and pseudo-differential DTC techniques, we achieved the lowest jitter without using DPD techniques.”

This innovative design has the potential to lead to technical improvements across many applications where fractional-N PLLs are a mainstay.