Two innovative design techniques have significantly improved the performance of fractional-N phase-locked loops (PLLs), Tokyo Tech scientists report. The proposed method aims to minimize unwanted signals known as fractional spurs that typically plague PLLs used in many modern radar systems and radio transceivers. These efforts could open the door to technological improvements in wireless communications, self-driving cars, and surveillance and tracking systems in the 5G era and beyond.
Many emerging and evolving technologies, such as self-driving cars, target tracking systems, and remote sensors, rely on the fast, error-free operation of wireless data transceivers and radar systems. In these applications, phase-locked loops (PLLs) are key components that help synthesize, modulate, and synchronize oscillating signals. Therefore, eliminating or minimizing sources of PLL error is essential to improving overall system performance.
The main enemy of fractional-N PLLs is a common type of PLL that offers superior resolution and flexible control over frequency, jitter, and fractional spurs. “Jitter” refers to the overall deviation of the synthesized oscillation from ideal timing. Fractional spurs, on the other hand, are unwanted signals resulting from the periodicity of errors. To cancel quantization errors, digital PLLs typically use a component called a digital time converter (DTC), but imperfections in the DTC due to so-called “integral nonlinearity (INL)” can ultimately appears as a fractional spur that degrades the Noise is generated at the output of the PLL.
In a recent study, a Tokyo Institute of Technology (Tokyo Tech) research team led by Professor Kenichi Okada sought to address these issues through the development of two innovative design techniques that lead to low spurious fractional-N PLLs. Their work was published in the proceedings of the 2024 IEEE International Solid-State Circuits Conference (ISSCC).
The first proposed technique involves the use of cascading fractional dividers. This method splits the frequency control word (FCW), the internal PLL signal that controls the output frequency, into two parts, both of which are far from integer values. The underlying logic is that for far-integer FCW, fractional spurs occur at high frequencies in the PLL, and the high-frequency components are naturally removed by the inherent behavior of the PLL (Figure 1). Notably, this approach does not include digital predistortion (DPD) techniques, which introduce complexity and introduce phase-lock delays.
The second proposed approach revolves around pseudo-differential DTC to avoid the pitfalls of standard DTC implementations (Figure 2). “Traditionally, his DTC designs had tough trade-offs between DTC power, delay range, noise, and INL, which limited the minimum achievable fractional spur level,” Professor Okada explains. To address this issue, researchers pointed out that the nonlinearity of DTC even contains a symmetric component. Therefore, they implemented the functionality of a single DTC using two half-range DTCs with the same even symmetrical INL in differential operation. As a result, these INLs were naturally canceled by subtraction in the phase detector of the PLL.
The team tested the idea by implementing the proposed digital PLL using a 65 nm CMOS process that requires only 0.23 mm of active circuit area.2. The researchers noticed several advantages by comparing the performance of their device with other state-of-the-art designs. “By suppressing fractional spurs, the integrated PLL jitter was reduced from 243.5 fs to 143.7 fs,” Professor Okada emphasizes. “Thanks to the proposed cascaded fractional divider and pseudo-differential DTC techniques, we achieved the lowest jitter without using DPD techniques.”
With any luck, this innovative design will lead to technical improvements across many applications where fractional-N PLLs are a mainstay.
Some of the results of this research were obtained through commissioned research (No.JPJ012368C00801) from the National Institute of Information and Communications Technology (NICT).
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About Tokyo Institute of Technology
As Japan’s leading science and engineering university, Tokyo Institute of Technology stands at the forefront of research and higher education. Tokyo Tech researchers excel in a wide range of fields, from materials science to biology, computer science, and physics. Founded in 1881, Tokyo Tech admits more than 10,000 undergraduate and graduate students annually who go on to become scientific leaders and industry’s most sought-after engineers. The Tokyo Tech community embodies the Japanese philosophy of “manozukuri,” meaning “technical ingenuity and innovation,” and strives to contribute to society through impactful research.
https://www.titech.ac.jp/english/
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