Synopsys CEO Sassine Ghazi will be the first SNUG CEO to take the stage, and will be joined by Nvidia CEO Jensen Huang to discuss collaboration between the two companies and more.
I had no idea that Synopsys and Nvidia had such a close relationship. Apparently, according to Jensen, when the GPU company was in its infancy, Synopsys used to deliver box after box of manuals to his Nvidia headquarters (just his one-room office) (yes, I remember that) (In the past, it was printed in thick books!) . If the next chip failed and needed to be taped out again, the startup would be stuck, so they needed Synopsys’ simulation and design tools to make that possible remotely. The rest, as they say, is history.
Silicon Complexity: On the Road to 1 Trillion Transistors and 1 Angstrom
Jensen and Sassine opened the conference by talking about the challenges facing chip designers, from chip complexity to chiplets to the intersection of system design and silicon design. The slides below summarize what the two companies have accomplished together, delivering 10-15x improvements across chip design workflows and now moving into generative AI and system software.
Synopsys has already significantly improved design capture with DSO.AI, the company’s first AI-enhanced design platform, and expanded the use of reinforcement learning into verification, testing, and analog spatial design. These AI-driven tools are used in tapeouts for hundreds of customers, delivering over 10% performance, power, and area (PPA) improvements, up to 10x faster turnaround times, and improved verification coverage. improved by two orders of magnitude. 4x faster testing and 4x faster analog circuit optimization with the same coverage when compared to optimization without AI. We also added AI to our data analytics platforms such as Design.da, Silicon.da, and Fab.da to create better PPAs and higher manufacturing yields.
Synopsys also built Synopsys.ai, a generative AI solution that helps junior members of chip design teams get answers to questions about a myriad of AI tools and cloud services products. At Synopsys, we don’t call something “generative AI” unless it’s built using a large-scale language model. For example, the .ai family is built using reinforcement learning. Reinforcement learning is an old technique that is still cutting edge in solving game theory problems such as location and routes.
The company is currently applying AI to 3D chip design. 3D design comes with all kinds of thermal design challenges, and new platform architect MultiDai and his 3DSO.ai increase productivity by as much as 10x, helping you solve thermal problems using native thermal solvers. Solve your challenges in just a few hours. It’s not a day.
Sassine also introduced new hardware, the ZeBu EP2 emulation and prototyping platform, which can emulate chips up to an unprecedented scale of 5.6B gate sizes. The new ZeBu emulator is used for software startup, software/hardware verification, and power/performance analysis. Currently, no one designs chips by emulating the logic and layout. The design is too complicated. It’s rare now to hear of a chip that required more than one tapeout, but ten years ago it was an unheard of feat.
Staying in the hardware-assisted verification (HAV) space, Synopsys also launched the HAPS®-100 12 system, Synopsys’ highest capacity and density FPGA-based prototyping system that combines fixed and flexible interconnects. . This is especially useful for prototyping large designs. Many FPGAs are needed, including multi-die systems and large SoCs. Available now, this new prototyping system shares a common hardware platform with the Synopsys ZeBu EP2.
Hyperconvergence: The next EDA frontier
Finally, Sassine touched on the concept of hyperconvergence. The idea is that there is still a lot of optimization improvement to be made at the intersection of the various layers of the EDA stack. By applying AI to this level of abstraction and models, these hidden PPA opportunities can be uncovered and addressed. AI at this level is coupled in a tightly coupled system. AI can search a wider space across these layers and free “trapped” PPAs for further optimization. While it’s too early to quantify the benefits of hyperconvergent AI, Synopsys already has several customers testing the concept and model and expects to see some results soon.
conclusion
Synopsys believes these are journeys to increasingly automate mechanical engineering tasks and improve the performance, power, and cost of complex chip design and manufacturing. Talented and experienced design engineers will be able to focus on the work that only they can do, and work will increasingly be done at the architectural design and software level. Perhaps his 20% of “simple” chips, or those being redesigned for new manufacturing process nodes, could be designed entirely by AI under the supervision of a few engineers. Additionally, inference software platforms like Nvidia NIM will continue to provide designers with more options.
It’s a great time to be a chip designer.
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disclosure: This article expresses the opinions of the author.
It should not be taken as advice to buy or invest in the companies mentioned. Cambrian AI Research is fortunate to work with many, if not most, semiconductor companies, including Blaize, BrainChip, Cadence Design, Cerebras, D-Matrix, Eliyan, Esperanto, GML, Groq, IBM, Intel, Mythic, NVIDIA, and Qualcomm. We welcome you as a customer. Technologies, Si-Five, SiMa.ai, Synopsys, Ventana Microsystems, Tenstorrent, and numerous investment clients. The Company does not have an investment position in any of the companies mentioned in this article and has no plans to begin investing in any of the companies mentioned in this article in the near future. For more information, please visit our website https://cambrian-AI.com.
